1. Field of the Invention
The present invention relates to a MOS semiconductor integrated circuit device adapted to realize low power dissipation by interrupting the power to a circuit at standby time.
2. Description of the Related Art
In the recent semiconductor trade, as the market of portable electronic equipment has expanded, the demand has increased for developing MOS semiconductor integrated circuit devices adapted to effect a reduction in power dissipation. Above all, static random access memories (SRAMs) have become larger and larger every year in their area on LSI chips. From the point of view of power dissipation, therefore, the importance of lowering the supply voltage of the SRAMs has increased. The row decoder circuit in peripheral circuits of the SRAM macro accounts for most of the leakage current which determines standby power dissipation of an LSI chip containing an SRAM macro.
The row decoder circuit includes a prebuffer circuit and the last-stage main buffer circuit. A word line is selectively driven by an output signal of the main buffer circuit.
In general, in the row decoder circuit, the word lines are fixed at a low level in potential at standby time, thereby preventing the word lines from shifting from the low level due to the effect of noise or the like.
At standby time, various leakage currents are generated in the row decoder circuit. In general, P- and N-channel MOS transistors that constitute the main buffer circuit are large in device size. For this reason, subthreshold leakage and gate leakage in the main buffer circuit form the main leakage current sources at standby time, to which subthreshold leakage in the prebuffer circuit is added. Thus, making provisions for such leakage currents allows the leakage current in the row decoder circuit to be reduced.
As for provisions for leakage in the row decoder circuit, some research has already been carried out in various institutions. The important point regarding the provisions for leakage in the row decoder circuit is that the word lines must be fixed at 0 volts at standby time as described previously. Noise on the word lines might cause memory cells to be selected in error, leading to data destruction. Therefore, the word lines must be fixed at 0 volts at standby time including mode transition time.
A conventional row decoder circuit intended to reduce the standby leakage current is one which is described in document 1 (“A 300 MHz 25 uAMb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Model for Mobile-Phone Application Processor”, M. Yamaoka, ISSCC 2004). In the row decoder circuit described in document 1, current-cutoff N-channel MOS transistors are inserted in the middle of current paths on the ground potential side in circuits other than the last-stage buffer circuit to thereby interrupt the power. In the last-stage buffer circuit, the word lines must be fixed at 0 volts at standby time. For this reason, it is impossible to insert a current-cutoff N-channel MOS transistor in the middle of the current path on the ground potential side for the purpose of interrupting the power. In the last-stage buffer circuit, therefore, a current-cutoff P-channel MOS transistor is inserted in the middle of the current path on the supply voltage Vdd side to thereby interrupt the power.
In the row decoder circuit described in document 1, however, the gate-to-source voltage Vgs of the N-channel MOS transistor in the last-stage buffer circuit become VDD (supply voltage) at standby time; thus, the gate leakage current of the N-channel MOS transistor cannot be reduced. This will particularly become a problem when the effect of gate leakage increases in the next-generation MOS semiconductor integrated circuit devices.
Another conventional row decoder circuit intended to reduce the standby leakage current is one which is described in document 2 (A 90 nm Low Power 32 K-Byte Embedded SRAM with Gate Leakage Suppression Circuit for Mobile Application”, Koji Nii et al., 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 247–250 (FIG. 7b)). In the row decoder circuit described in document 2, the last-stage buffer circuit is composed of a P-channel MOS transistor and an N-channel MOS transistors. A transfer gate is added between the gate of the N-channel MOS transistor and the output node of the prebuffer circuit preceding the last-stage buffer circuit. When the word line is on standby, the transfer gate is turned off by a signal on the word line, causing the gate of the N-channel MOS transistor to go into the floating state. In the floating state, the gate voltage of the N-channel MOS transistor drops gradually due to the gate leakage. Thereby, the gate-to-source voltage Vgs of the N-channel MOS transistor drops, suppressing the generation of gate leakage current.
In the row decoder circuit described in document 2, however, subthreshold leakage current flows in the P-channel MOS transistor in the last-stage buffer circuit. Since the transistors in the last-stage buffer circuit are large in device size as described previously, a large subthreshold current flows in the standby state.
Thus, in the conventional MOS semiconductor integrated circuit devices intended to reduce power dissipation, both the gate leakage current and the subthreshold leakage current cannot be reduced and hence a sufficient leakage current reducing effect cannot be attained.